(1) Field of the Invention
The present invention relates to a metal-oxide semiconductor (MOS) static-type semiconductor memory device.
(2) Description of the Prior Art
Generally, in a MOS static-type semiconductor memory device, one static-type memory cell constructed as a flip-flop is provided at each intersection of word line and bit line pairs, and one word line and one bit line are selected by address means, such as row address buffers, row address decoders, column address buffers, column address decoders, and the like, so that one memory cell is selected. In this case, the actual selection of one word line is performed by a word-line driver clock signal after the row address decoders determine a selected row. Thus, when one word line is selected, a large number of non-selected memory cells connected to the selected word line are also electrically connected to corresponding bit line pairs. For example, in a 16K bit memory, 127 non-selected memory cells are electrically connected to corresponding bit lines. As a result, current flows from the corresponding bit lines into these memory cells. The dissipation of power of a static semiconductor memory device is mainly due to the driving of such a bit line load.
In the prior art, in a selected state, i.e., after external signals (such as a row access strobe signal) are received, the word-line driver clock signal becomes high so that at least one of the word lines is always in a selected state. Therefore, the dissipation of power is remarkably large.
On the other hand, the bit line pairs are connected, via load transistors, to a power supply. Therefore, in a non-selected mode, the bit line pairs are charged at a predetermined potential by the power supply. However, in a selected mode, such as a read mode, memory cells connected to a selected word line are electrically connected to the corresponding bit line pairs so that current flows from the bit lines into the memory cells. As a result, a difference in potential between the bit lines is generated, the difference in potential is sensed or amplified by a sense amplifier, and data output is transmitted, via an output buffer, to the exterior. At this time, in order to generate a suitable difference in potential between the bit lines, a suitable relationship is formed between the transconductance (g.sub.m) of the transistors within the memory cells and the transconductance g.sub.m of the load transistors. Therefore, it is impossible to increase or decrease the transconductance (g.sub.m) of the load transistors.
Recently, much progress has been made in integrated MOS static-type semiconductor memory devices, and, accordingly, the size of the memory cells has been reduced. In this case, naturally, since the transconductance (g.sub.m) of the transistors within the memory cells is reduced, the transconductance (g.sub.m) of the load transistors is also reduced. However, since the capacitance of the bit lines is large, the driving power of the memory cells for the bit lines is small. Accordingly, the speed of change of the bit line potential becomes small, thereby reducing the read operation speed.